(1) Field of the Invention
This invention relates to a method to deposit by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,225,221 B1 entitled “Method to Deposit a Copper Seed Layer for Dual Damascene Interconnects” granted May 1, 2001 to Ho et al. describes a method of depositing a copper seed layer in the manufacture of an integrated circuit device. The copper seed layer is thin and conformal for subsequent electroless plating of copper. A dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer of tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer.
U.S. Pat. No. 6,305,314 B1 entitled “Apparatus and Concept for Minimizing Parasitic Chemical Vapor Deposition During Atomic Layer Deposition” granted Oct. 23, 2001 to Sneh et al. teaches a method and apparatus for avoiding contamination of films deposited in layered depositions, such as Atomic Layer Deposition (ALD) and other sequential chemical vapor deposition (CVD) processes. The CVD deposited contamination of ALD films is prevented by use of a pre-reaction chamber that effectively causes otherwise-contaminating gaseous constituents to deposit on wall elements of gas-delivery apparatus prior to entering the ALD chamber.
U.S. Pat. No. 6,008,102 entitled “Method of Forming a Three-Dimensional Integrated Inductor” granted Dec. 28, 1999 to Alford et al. describes a method of fabricating a three-dimensional inductor coil is fabricated. The fabrication process includes the steps of: depositing a first photoresist layer, forming a trench therein, and filling the trench with electroplated metal. A second photoresist layer is deposited, and first and second trenches are formed therein and filled with electroplated metal. A third photoresist layer is deposited and a trench formed therein, and then filled with electroplated metal. The first, second, and third photoresist layers are then removed to expose a multi-loop inductor coil.
U.S. Pat. No. 6,329,234 B1 entitled “Copper Process Compatible CMOS Metal-Insulator-Metal Capacitor Structure and Its Process Flow” granted Dec. 11, 2001 to Ma et al. teaches that in many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process.
U.S. Pat. No. 6,146,458 entitled “Molecular Beam Epitaxy Method” granted Nov. 14, 2000 to Hooper et al. describes a method of growing a layer of Group III nitride material on a substrate by molecular beam epitaxy that includes the steps of: (i) disposing a substrate in a vacuum chamber, (ii) reducing the pressure in the vacuum chamber to a pressure suitable for epitaxial growth by molecular beam epitaxy, (iii) supplying ammonia through an outlet of a first supply conduit into the vacuum chamber so that the ammonia flows towards the substrate; and (iv) supplying a Group III element in elemental form through an outlet of a second supply conduit into the vacuum chamber so that said Group III element flows towards the substrate. The method causes a layer containing Group III nitride to be grown on the substrate by molecular beam epitaxy.
U.S. Pat. No. 6,042,652 entitled “Atomic Layer Deposition Apparatus for Depositing Atomic Layer on Multiple Substrates” granted Mar. 28, 2000 to Hyun et al. describes an atomic layer deposition (ALD) apparatus capable of depositing a thin film on a plurality of substrates. The atomic layer deposition apparatus includes: a vacuum chamber, a reactor installed in the vacuum chamber, having a plurality of modules which can he assembled and disassembled as desired. A plurality of stages as spaces are partitioned by assembling the plurality of modules. Openings allow each stage to receive one substrate. Also, there is a plurality of gas supply lines installed in the modules, for injecting gases from a gas supply portion into the stages.